/**
  ******************************************************************************
  * @file    set_clock.c
  * @author  Hanif Rizal
  * @version V1.0.0
  * @date    03-Maret-2013
  * @brief   ATXmega Clock access routine
  *              
  *  @verbatim
  *  
  *          ===================================================================
  *                                 How to use this driver
  *          ===================================================================              
  *   
  *  @endverbatim
  *    
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2013 Vibration Monitoring System TEAM</center></h2>
  ******************************************************************************
  */
#include "set_clock.h"

void Init_Clock_32MHz(void)
{
	CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc; //No Division CLK_PER=CLK_CPU;
	OSC.CTRL = OSC_RC32MEN_bm; /* start 32MHz RC oscillator */
	while (!(OSC.STATUS & OSC_RC32MRDY_bm)); /* wait for ready */
	CCP = CCP_IOREG_gc; /* allow changing CLK.CTRL */
	CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* system clock is internal 32MHz RC */
	
	//Activate DFLL in ATXMEGA
	OSC.DFLLCTRL = 0x00;
	//DFLLRC32M_COMP0 = 0x3D;
	DFLLRC32M_COMP1 = 0x12;
	DFLLRC32M_COMP2 = 0x7A;
	//DFLLRC2M_COMP2 = 0x7A;
	DFLLRC32M_CTRL = DFLL_ENABLE_bm;

}